This invention relates generally to semiconductor devices and more particularly to a lateral superlattice device providing quantum well transport effects.
Semiconductor devices having a superlattice structure in which there is a periodic variation in semiconductor composition is now generally known, having been shown and described, for example, in U.S. Pat. Nos. 3,626,257 and 3,626,328 which issued to Leo Esaki, et al. on Dec. 7, 1971. The layered superlattice structure disclosed therein comprises a one dimensional transport device that is formed by either doping or alloying techniques. The doping method of fabricating a superlattice structure involves epitaxially growing a semiconductor material which is periodically doped so as to produce alternating multi-thin layers having different conductivity types. A fabrication system which is particularly adapted to provide these ultra-thin, well defined multi-layered semiconductor structures comprises a process called molecular beam epitaxy (MBE) wherein automatically smooth surfaces and extremely sharp boundaries at the interface of two closely lattice matched semiconductors can be produced with a minimum number of defects. The technique of molecular beam epitaxy is well known and has been disclosed, for example, in the publication "Structures Grown By Molecular Beam Epitaxy", L. L. Chang, et al., J. Vac. Sci. Technology, Vol. 10, No. 5, September/October, 1973, p. 655. Another known fabrication technique involves the process of metalo-organic chemical or vapor deposition (MOCVD) which has been disclosed by N. Holonyak, in the Journal of Applied Physics, 1978, Vol. 49, p. 5392.
In U.S. Pat. No. 4,103,312, entitled, "Semiconductor Memory Devices", which issued to L. L. Chang, et al. on July 25, 1978, there is disclosed a multi-layered sandwich type heterostructure comprising alternating layers of different semiconductor materials forming a periodic structure and which is adapted to provide a three dimensional confinement of electrons and holes in the device.
Additionally, a multi-layered semiconductor heterostructure wherein potential wells are created between layers is disclosed in U.S. Pat. No. 4,257,055, entitled, "Negative Resistance Heterojunction Devices", which issued to K. Hess, et al. on Mar. 17, 1981. There an inner layer exhibits high charge carrier mobility and a relatively narrow band gap characteristic while the outer sandwich layers exhibit low charge carrier mobilities and a larger band gap characteristic and is operable such that under quiescent conditions the charge carriers of the outer sandwich layers reside in the inner layer due to the potential well created by the band gap difference between the layers. The application of an appropriate electrical field to the central layer, aligned with the interface between the layers, causes a very rapid transfer of electrons residing therein to the outer sandwich layers, with the resulting transfer providing a negative resistance characteristic.
It is an object of the present invention, therefore, to provide an improvement in semiconductor superlattice structures.
It is another object of the present invention to provide a two dimensional lateral superlattice structure within a single layer of semiconductor material.
Yet another object of the present invention is to provide a multi-dimensional superlattice structure in a single planar epitaxial layer of semiconductor material.